Vol 8, No 1 (2017) > Electrical, Electronics and Computer Engineering >

Dual Material Pile Gate Approach for Low Leakage Finfet

Sanjay S. Chopade, Dinesh V. Padole

 

Abstract: FinFET (Fin Field-Effect
Transistor) technology has recently seen a major increase in adoption
for use in integrated circuits because of its high immunity to short channel
effects and its further ability to scale
down. Previously, a major research contribution was made to reduce the leakage current in the
conventional bulk devices. So many different alternatives like bulk isolation and oxide isolation are all having some pros and
cons. Here in this paper, we present a novel pile gate FinFET structure to
reduce the leakage current, as compared with Bulk FinFET without using any pstop implant or
isolation oxide as in the
Silicon-on-Insulator (SOI). The major advantage of this type of
structure is that there is no need of high substrate doping, a 100% reduction in the
random dopant fluctuation (RDF) and an increase in the ION/IOFF
value. It can be very useful to improve the drain-induced barrier lowering (DIBL) at smaller
technological nodes. All the work is supported by 3D TCAD simulations, using Cogenda TCAD.
Keywords: Bulk FinFET; Charge accumulation; Leakage current; Lower doping; Pile Gate FinFET

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References


Asenov, A., 1998. Random Dopant Induced Threshold Voltage Lowering and Fluctuations in sub-0.1 μm MOSFET’s: A 3-D “Atomistic” Simulation Study. IEEE Transactions on Electron Devices, Volume 45(12), pp. 2505–2513

Asenov, A., Slavcheva, G., Brown, A.R., Davies, J.H., Saini, S., 2001. Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in sub-100 nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study. IEEE Transactions on Electron Devices, Volume 48(4), pp. 722–729

Bin, Y., Leland, C., Ahmed, S., Haihong, W., Bell, S., Chih, Y., Tabery, C., Chau, H., Qi, X., Tsu, K., Bokor, J., Hu, C., Ming, L., Kyser, D., 2002. FinFET Scaling to 10 nm Gate Length. In: International Electron Devices Meeting 2002, San Francisco, 8-11 December, USA, pp. 251–254

Colinge, J.P., 2007. FinFETs and Other Multi-Gate Transistors. United States: Springer-Verlag New York Publications

Cogenda User’s Manual, 2010. Available online at: http://www.cogenda.com

Huang, X., Lee, W., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y., Asano, K., Subramanian, V., King, T., Bokor, J., Hu, C., 1999. Sub 50-nm FinFET: PMOS. Electron Devices Meeting, IEDM '99. Technical Digest. International, pp. 67-69

Hussain, M.M., Smith, C.E., Harris, H.R., Young, C.D., Tseng, H.H., Jammy, R., 2010. Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses into High-k/Metal Gates CMOS FinFETs for Multi-Vth Engineering. IEEE Transactions on Electron Devices, Volume 57(3), pp. 626–631

Liao, Y.B., Hsu, W.C., Chiang, M.H., Li, H., Lin, C.L., Lai, Y.S., 2011. Optimal Device Design of FinFETs on a Bulk Substrate. In: Proceedings of the 4th IEEE International NanoElectronics Conference 2011, Tao-Yuan, 21-24 June, Taiwan, pp.1-2

Moshgelani, F., Al-Khalili, D., Rozon, C., 2012. Ultra Low Leakage Structures for Logic Circuits using Symmetric and Asymmetric FinFETs. Journal of Electrical and Computer Engineering, Volume 2013, pp. 385-388

Pal, P.K., Kaushik, B.K., Dasgupta, S., 2013. High-Performance and Robust SRAM Cell Based on Asymmetric Dual-k Spacer FinFETs. IEEE Transactions on Electron Devices, Volume 60(10), pp. 3371–3377

Pal, P.K., Kaushik, B.K., Dasgupta, S., 2015. Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis. IEEE Transactions on Electron Devices, Volume 62(4), pp.1105-1112

Roy, K., Mukhopadhyay, S., Mahmoodi, H., 2003. Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. In: Proceedings of the IEEE, Volume 91(2), pp. 305–327

Singh, N., Buddharaju, K.D., Manhas, S.K., Agarwal, A., Rustagi, S.C., Lo, G.Q., Balasubramanian, N., Kwong, D.L., 2008. Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications. IEEE Transactions on Electron Devices, Volume 55(11), pp. 3107–3118

Su, P.H., Li, Y., 2015. Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices. IEEE Transactions on Semiconductor Manufacturing, Volume 28(2), pp. 193–199

Xu, M., Zhu, H., Zhao, L., Yin, H., Zhong, J., Li, J., Zhao, C., Chen, D., Ye, T., 2015. Improved Short Channel Effect Control in Bulk FinFETs with Vertical Implantation to Form Self-Aligned Halo and Punch-Through Stop Pocket. IEEE Electron Device Letters, Volume36(7), pp. 648–650

Yoshida, E., Miyashita, T., Tanaka, T., 2005. A Study of Highly Scalable DG-Fin DRAM. IEEE Electron Device Lett., Volume 26(9), pp. 655-657

ITRS. Available online at: http://www.itrs2.net/2013-itrs.html